High Speed and Area Efficient Matrix Multiplication Architecture on Xilinx Vertex2
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چکیده
Matrix multiplication is very important in many types of applications including image and signal processing and it depends on kernel operation. This paper presents three designs for matrix-matrix multiplication. These design reduced the requirement of hardware, increase the speed of operation which is required to different application requirements. These designs have been implemented on Xilinx Virtex-2. The proposed parallel-fixed-input and multiple-output (PPI-MO) structure saves 70% less energy than the existing structure.
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